b$.$ In our simple digital voltmeter, the outputs from the encoder will drive one of the segments of the $7-$segment display. In Figure $7,$ the $\text{'}$e$\text{'}$ segment is not illuminated by a logic $\text{'}0\text{'}$ and is illuminated by a logic $\text{'}1\text{'}.$

Note the inverting inputs of the two $5-$input AND gates. The 'e'segment is illuminated for displaying the digits $0$ and $2,$ while it is not illuminated for digits $1,3,4$ and $5.$ The bottom AND gate outputs logic $\text{'}1\text{'}$ when none of the comparator outputs are logic $\text{'}1\text{'}(5$ V $),$ i$.$e$.$ when Vin is $0$ V $.$ The top AND gate outputs logic $\text{'}1\text{'}$ when the outputs for comparators C$1$ and C$2$ are $5$ V $($logic $\text{'}1\text{'})$ and the outputs for comparators C$3,$ C$4$ and C $5$ are $0$ V $($logic $\text{'}0\text{'},$ or logic $\text{'}1\text{'}$ when inverted$).$

Using only inverters, $5-$input AND gates and a $5-$input OR gate in a similar way to Figure $5,$ give a circuit diagram that will illuminate the $\text{'}$a$\text{'}$ segment of the $7-$segment display for the corresponding digits between $0$ and $5.$ You may use inverting inputs as illustrated by the small circles on the AND gate inputs in Figure $5.$ Note that MultiSim Live does not use inverting inputs of logic gates.

$(6$ marks$)$

c$.$ Looking again at Figure $7,$ one can see that the two $5-$input AND gates used to illuminate the $\text{'}$e$\text{'}$ segment share equal values for some of the inputs, namely $\text{'}0\text{'}$ at inputs C$3,$ C$4,$ and C$5.$ This means that the $\text{'}$e$\text{'}$ segment is illuminated when C$3=\text{'}0\text{'}$ AND C$4=\text{'}0\text{'}$ AND C$5=\text{'}0\text{'},$ or in a compact form e $=$ C$3\text{'}$C$4\text{'}$C$5\text{'},$ implemented as one $3-$input AND gate with inverters at its inputs for the signals C$3,$ C$4,$ and C$5.$ This gives an idea how to reduce the number of gates and inputs for the decoder. Using this approach, give a similar implementation with a reduced number of gates and inputs for the decoder for the $\text{'}$a$\text{'}$ segment. You may find it easier to use a truth table and$/$or Karnaugh map in this part. Comment how this compares to the straightforward approach from Figure $7.$

$(8$ marks$)$

Hint: If you use a five$-$input Kamaugh map, for inputs $\backslash ($ A$,$ B$,$ C$,$ D $\backslash ),$ and $\backslash ($ E $\backslash ),$ it will have the following form: