Below is a list of 32-bit memory references in a byte addressable CPU, given as word address in decimal.

6, 191, 22, 79, 159, 241, 102

a)What is the hex address of each address? (format is the following: 0x33557794, 0x11223348, etc.)

b)For a directed-mapped cache comprises of 8 cache blocks of 1 one-word blocks, what are the cache tags for each of these addresses? (For this exercise, the format of the tags should be 32-bits in hex, or 8 hex characters. The lower bits that are not associated with the tag should be inserted with 0s. (format example only and is not related to the answer is the following: 0x33557700, 0x11223300, etc.))

c) For a directed-mapped cache comprises of 8 cache blocks of 1 one-word blocks, what are the block address or index for each of these addresses? (The format should be in binary such as 1001b, 1100b, 0001b, etc.)

d) For 2-way set associative cache of 4 sets comprising of blocks of one-world blocks. What are the cache tags for each of these addresses? (For this exercise, the format of the tags should be 32-bits in hex, or 8 hex characters. The lower bits that are not associated with the tag should be inserted with 0s. (format example only and is not related to the answer is the following: 0x33557700, 0x11223300, etc.))

e) For the 2-way set associative cache above, what would be the addresses associated with set 10b for position 1 and 2 of this set at the end of the address stream above assuming LRU replacement algorithm? Assume this cache is completely empty at the start, and the first value of a set is placed in position/element 1 of the set. (format, the complete decimal address such as 16, 32)