Below is the Systemlnit Function in our system stm32f4xx.c file: void SystemInit (void) FPU settings tif FPU PRESENT 1) & FPU USED 1) SCB->CPACR (3UL 10 2) I (3UL 11 2) set CP10 and CP11 Full Access endif Reset the RCC clock configuration to the default reset state Set HSION bit RCC- CR. I (uint 32 t) 0x000000001 Reset CFGR register RCC- CFGR OOOOOOOO Reset HSEON, CSSON and PLLON bits RCC->CR & (uint 32 t) OxFEF 6FEFF: Reset PLLCFGR register RCC- PLLCE GR. Ox24 003010 Reset HSEBYP bit RCC- CR. & (uint 32 t) OxEEEBEEEE Disable all interrupts RCC- CIR. OxOOOOOOOO atif defined (DATA IN ExtSRAM) II defined DATA IN Ext SDRAM) SystemInit tl. #endif DATA IN ExtSRAM II DATA IN Ext SDRAM Configure the Vector Table location add offset address ifdef VECT TAB SRAM. SCB->vTOR SRAM BASE I VECT TAB OFFSET: Vector Table Relocation in Internal SRAM #else SCB- TOR. FLASH BASE I VECT TAB OFESET: Vector Table Relocation in Internal FLASH endif Below is the Systemlnit Function in our system stm32f4xx.c file: void SystemInit (void) FPU settings tif FPU PRESENT 1) & FPU USED 1) SCB->CPACR (3UL 10 2) I (3UL 11 2) set CP10 and CP11 Full Access endif Reset the RCC clock configuration to the default reset state Set HSION bit RCC- CR. I (uint 32 t) 0x000000001 Reset CFGR register RCC- CFGR OOOOOOOO Reset HSEON, CSSON and PLLON bits RCC->CR & (uint 32 t) OxFEF 6FEFF: Reset PLLCFGR register RCC- PLLCE GR. Ox24 003010 Reset HSEBYP bit RCC- CR. & (uint 32 t) OxEEEBEEEE Disable all interrupts RCC- CIR. OxOOOOOOOO atif defined (DATA IN ExtSRAM) II defined DATA IN Ext SDRAM) SystemInit tl. #endif DATA IN ExtSRAM II DATA IN Ext SDRAM Configure the Vector Table location add offset address ifdef VECT TAB SRAM. SCB->vTOR SRAM BASE I VECT TAB OFFSET: Vector Table Relocation in Internal SRAM #else SCB- TOR. FLASH BASE I VECT TAB OFESET: Vector Table Relocation in Internal FLASH endif