Bonus - Reverse Engineering (30pts) (a) Reverse engineer the behavior of the sequential circuit shown below. Show the state machine table and the FSM state machine diagram. (10pts) a clk s1 Combinational Logic SO State Register n1 no y (b) In edaplayground, write and verify the verilog for the controller. Include screenshots of the FSM cycling through each state. Explain why the waveform is correct. Also include your verilog testbench. sv and design.sv in a folder called Hw03_bonus. (20pts)