Part (B) Counter. (50 pts) Build a counter that counts up from 0 to 64 by...

 

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Part (B) Counter. (50 pts) Build a counter that counts up from 0 to 64 by using a 6-bit binary counter. A user must be given an option to choose between a counting value or a decimal equivalent of a 6-bit binary input (given by the user). It means that seven segment either counts one by one or shows the decimal value of user input. While the display is showing the user input, the counter should continue the counting even though its counting is not displayed. There should be also the reset option for the counter. The number should be displayed on a 7-segment display in this manner: '0000' → 0001' → '0005' → ... → '0015' → '0055' ... You will have to use some parts of the circuit you built in the lab 7. The counting speed should be about 1 second. This can be achieved by dividing a clock. In default, the counter should be counting continuously until a reset is activated, which will make the counting value to be 0. When the reset is deactivated, it should start counting again from 0. For example, when the user input is '001011'. CLK:1 S:0 Display: 0000 CLK:2 S:0 Display: 0001 CLK:3 S:0 Display: 0002 CLK:4 S:1 Display: 0011 CLK:5 S:1 Display: 0011 CLK:6 S:0 Display: 0005 CLK:7 S:0 Display: 0006 Supplementary information: 1. Clock divider. A clock frequency of a Basys3 board is 100 MHz. For specific applications such as a counting process, it is necessary to lower the frequency so that the process can be seen with human eyes. In the IP catalog, there is a clock divider. How does it work? There is a Size parameter, it works as a prescalar. For instance, let us say that the board has a clock of 1 MHz, and we need a 5 kHz signal. Then, 1 MHz/5 kHz= 20000 is a prescalar, which can be entered as a Size parameter. clkin xup_clk_divider_1 XILINX UNIVERSITY clkin PROGRAM clkout clkout xup_clk_divider Part (B) Counter. (50 pts) Build a counter that counts up from 0 to 64 by using a 6-bit binary counter. A user must be given an option to choose between a counting value or a decimal equivalent of a 6-bit binary input (given by the user). It means that seven segment either counts one by one or shows the decimal value of user input. While the display is showing the user input, the counter should continue the counting even though its counting is not displayed. There should be also the reset option for the counter. The number should be displayed on a 7-segment display in this manner: '0000' → 0001' → '0005' → ... → '0015' → '0055' ... You will have to use some parts of the circuit you built in the lab 7. The counting speed should be about 1 second. This can be achieved by dividing a clock. In default, the counter should be counting continuously until a reset is activated, which will make the counting value to be 0. When the reset is deactivated, it should start counting again from 0. For example, when the user input is '001011'. CLK:1 S:0 Display: 0000 CLK:2 S:0 Display: 0001 CLK:3 S:0 Display: 0002 CLK:4 S:1 Display: 0011 CLK:5 S:1 Display: 0011 CLK:6 S:0 Display: 0005 CLK:7 S:0 Display: 0006 Supplementary information: 1. Clock divider. A clock frequency of a Basys3 board is 100 MHz. For specific applications such as a counting process, it is necessary to lower the frequency so that the process can be seen with human eyes. In the IP catalog, there is a clock divider. How does it work? There is a Size parameter, it works as a prescalar. For instance, let us say that the board has a clock of 1 MHz, and we need a 5 kHz signal. Then, 1 MHz/5 kHz= 20000 is a prescalar, which can be entered as a Size parameter. clkin xup_clk_divider_1 XILINX UNIVERSITY clkin PROGRAM clkout clkout xup_clk_divider

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To implement the counter described in Part B you can use Verilog code for the ... View the full answer