Build a Full Adder using two Half Adders and an OR gate. Again, a skeleton of...

 

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Build a Full Adder using two Half Adders and an OR gate. Again, a skeleton of the Verilog description of the full adder is provided, with some details erased. Your task is to fill in the blanks. Be sure that your Verilog description exactly matches the circuit below. module fulladder (S. C, x, y, cin); input x, y, cin; output S, C; //internal signals wire S1, D1, D2; //Instantiate the half adders halfadder HA1 (S1, D1, halfadder HA2 (______ or U3(______ endmodule cin X Half Adder 1 HA1 $1 D1 SI > DI Half Adder 2 HA2 D2 D2 U3 C U3 S Implementation of Full Adder with Two Half Adders and an OR Gate Build a Full Adder using two Half Adders and an OR gate. Again, a skeleton of the Verilog description of the full adder is provided, with some details erased. Your task is to fill in the blanks. Be sure that your Verilog description exactly matches the circuit below. module fulladder (S. C, x, y, cin); input x, y, cin; output S, C; //internal signals wire S1, D1, D2; //Instantiate the half adders halfadder HA1 (S1, D1, halfadder HA2 (______ or U3(______ endmodule cin X Half Adder 1 HA1 $1 D1 SI > DI Half Adder 2 HA2 D2 D2 U3 C U3 S Implementation of Full Adder with Two Half Adders and an OR Gate