A block diagram for a 16-bit 2€™s complement serial subtracter is given here. When St = 1, the registers are loaded and then subtraction occurs. The shift counter, C, produces a signal C15 = 1 after 15 shifts. V should be set to 1 if an overflow occurs. Set the carry flip-flop to 1 during load in order to form the 2€™s complement. Assume that St remains 1 for one clock time.
(a) Draw a state diagram for the control (two states).
(b) Write Verilog code for the system. Use two always blocks. The first always block should determine the next state and control signals; the second always block should update the registers on the rising edge of the clock. 

X(16) XIN(16) YP Full Y(16) adder YIN(16) Load Shift CA CB Carry FF CLK Control XO St ov YP FF C15 C(4)