Bypass network design: given the following ID$,$ EX$,$ MEM, and WB

pipeline configuration, draw all necessary MuxO and Muxl bypass

paths to resolve RAW data hazards. Assume that load instructions are

always separated by at least one independent instruction $[$possibly a

no$-$operation instruction $($NOP$)]$ from any instruction that reads the

loaded register $($hence you never stall due to a RAW hazard$).$P$2\mathrm{.}11$ Bypass network design: given the following ID$,$ EX$,$ MEM, and WB pipeline configuration, draw all necessary Mux$0$ and Mux$1$ bypass paths to resolve RAW data hazards. Assume that load instructions are always separated by at least one independent instruction $[$possibly a no$-$operation instruction $($NOP$)]$ from any instruction that reads the loaded register $($hence you never stall due to a RAW hazard$).$