$($c$)$ Stretch Activity

When performing computational operations it is often useful to be able to exe$-$

cute a sequence of operations, each one using the output of the previous step as

an input to the next step. For example to OR $3$ values x OR Y OR Z you might

first calculate x OR Y and then on the next step apply OR Z to the previous

output OR Y$.$

For this task adapt the circuit FALL so that it can combine a sequence of

operations defined by different values for f$\_(1)$ and f$\_(0)$ at each step, by enabling

the outputs F$\_($t$)$ and G$\_($t$)$ of step t to be used $($feedback$)$ as the inputs for the next

operation C$\_($t$+1)$ and D$\_($t$+1)$ for step t$+1.$ You should also add a further input

$($Load$)$ to the chip which when Load $=1$ will enable you to load new inputs to

C$\_($t$)$ and D$\_($t$)$ and when set to $0$ sets C$\_($t$+1)=$F$\_($t$)$ and D$\_($t$+1)=$G$\_($t$).$ The Load input

will allow you to manually set the values of C and D at the start and during

the sequence if required.

Call this chip FSEQ. You can test this chip using FSEQ.tst but may wish to

create further tests before submission.

You must only use the built$-$in AND, NAND, OR$,$ NOR, NOT, Mux, DMux,

XOR or DFF chips. My chip is fseq:

however, it is not passing the following test file:CHIP FSEQ $\{$

IN A$,$ B$,$ C$,$ D$,$ f$0,$ f$1,$ load;

OUT E$,$ F$,$ G;

PARTS:

$//$ Calculate the FALL operation

FALL$($A$=$A$,$ B$=$B$,$ C$=$Ct$,$ D$=$Dt$,$ f$0=$f$0,$ f$1=$f$1,$ E$=$newE, F$=$Ft$,$ G$=$Gt$)$;

$//$ Store the output of FALL operation into DFFs

DFF$($in$=$Ft$,$ out$=$storedF$)$;

DFF$($in$=$Gt$,$ out$=$storedG$)$;

$//$ Use Mux to decide whether to load new values or use stored values

Mux$($a$=$storedF, b$=$C$,$ sel$=$load, out$=$Ct$)$;

Mux$($a$=$storedG, b$=$D$,$ sel$=$load, out$=$Dt$)$;

$\}$ load FSEQ.hdl$,$

output$-$file FSEQ.out,

compare$-$to FSEQ.cmp$,$

output$-$list f$1\%$B$3\mathrm{.}1\mathrm{.}3$ f$0\%$B$3\mathrm{.}1\mathrm{.}3$ A$\%$B$3\mathrm{.}1\mathrm{.}3$ B$\%$B$3\mathrm{.}1\mathrm{.}3$ C$\%$B$3\mathrm{.}1\mathrm{.}3$ D$\%$B$3\mathrm{.}1\mathrm{.}3$ E$\%$B$3\mathrm{.}1\mathrm{.}3$ F$\%$B$3\mathrm{.}1\mathrm{.}3$ G$\%$B$3\mathrm{.}1\mathrm{.}3$;

set load $1,$

set f$11,$

set f$01,$

set A $1,$

set B $0,$

set C $1,$

set D $1,$

tick,

tock,

output;

set load $0,$

set f$10,$

set f$00,$

tick,

tock,

output;

set f$11,$

set f$01,$

tick,

tock,

output; Please help me to fix this chip