c$.$ You are asked to optimize a cache design for the given references. There are three direct$-$mapped cache

designs possible, all with a total of $8$ words of data: $C1$ has $1-$word blocks, $C2$ has $2-$word blocks, and $C3$ has

$4-$word blocks. In terms of miss rate, which cache design is the best? If the miss stall time is $25$ cycles, where

$C1$ has an access time of $2$ cycles, $C2$ takes $3$ cycles, and $C3$ takes $5$ cycles, which is the best cache design?

C$1$

$C2$

$C3$

Question $2$:

Caches are important to providing a high$-$performance memory hierarchy to processors. Below is a list of $32-$bit memory

address references, given as word addresses.

$3,180,43,2,191,88,190,14,181,44,186,253$

a$.$ For each of these references, identify the binary address, the tag, and the index given a direct mapped cache

with $16$ one$-$word blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty.

$16$ blocks means $4-$bits index therefore

b$.$ For each of these references, identify the binary address, the tag, and the index given a direct mapped cache

with two$-$word blocks and a total size of Sblocks. Also list if each reference is a hit or a miss, assuming the

cache is initially empty.

$8$ blocks means $3-$bits index, block, offset$=1$