B) Caches are important to providing a high-performance memory hierarchy to processors. Below is a list of 64-bit memory address references, given as word addresses. 003,0b4,02b,002,0bf,058,0be,00e,0b5,02c 0xa,0fd 1- For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with 16 one-word blocks. Also, list if each reference is a hit or a miss, assuming the cache is initially empty. 2- For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with two-word blocks and a total size of 8 blocks. Also, list if each reference is a hit or a miss, assuming the cache is initially empty. 3- You are asked to optimize a cache design for the given references. There are three direct-mapped cache designs possible, all with a total of 8 words of data: C1 has 1-word blocks, C2 has 2-word blocks, and C3 has 4-word blocks. In terms of miss rate, which cache design is the best? If the miss stall time is 25 cycles, and C1 has an access time of 2 cycles, C2 takes 3 cycles, and C3 takes 5 cycles, which is the best cache design? Many different design parameters are important to a cache's overall performance. Below are listed parameters for different direct-mapped cache designs. Cache Data Size: 32KiB Cache Block Size: 2 words Cache Access Time: 1 cycle