Cache simulator programming assignment with C programming. There will need to be three C files total, so please separate those programs in your answer. The names of those C files should be: valid.c, sim.c, and simulate.c

The goal of this assignment is to provide you a better understanding of caches. You are required to write a cache simulator using the C programming languages. The programs have to run on iLab machines and should be tested with the autograder. We are providing real program memory traces as input to your cache simulator. The format and structure of the memory traces are described below. Memory Access Traces The input to the cache simulator is a memory access trace, which we have generated by executing real programs. The trace contains memory addresses accessed during program execution. Your cache simulator will have to use these addresses to determine if the access is a hit, miss, and the actions to perform. The memory trace file consists of multiple lines. Each line of the trace file corresponds to a memory accesses performed by the program. Each line consists of multiple columns, which are space- separated.The first column reports the PC (program counter) when this particular memory access occurred. Second column lists whether the memory access is a read (R) or a write operation. And the last column reports the actual 48-bit memory address that has been accessed by the program. In this assignment, you only need to consider the second and the third columns (i e. you don't really need to know the PCs). Cache Simulator You will implement a cache simulator to evaluate different configurations of caches. It should be able to run with different traces files. The followings are the requirements for your cache simulator: 1. Simulate only one level cache L1 2. The cache size, associativity, and block size are input parameters. Cache size and block size are specified in bytes. The goal of this assignment is to provide you a better understanding of caches. You are required to write a cache simulator using the C programming languages. The programs have to run on iLab machines and should be tested with the autograder. We are providing real program memory traces as input to your cache simulator. The format and structure of the memory traces are described below. Memory Access Traces The input to the cache simulator is a memory access trace, which we have generated by executing real programs. The trace contains memory addresses accessed during program execution. Your cache simulator will have to use these addresses to determine if the access is a hit, miss, and the actions to perform. The memory trace file consists of multiple lines. Each line of the trace file corresponds to a memory accesses performed by the program. Each line consists of multiple columns, which are space- separated.The first column reports the PC (program counter) when this particular memory access occurred. Second column lists whether the memory access is a read (R) or a write operation. And the last column reports the actual 48-bit memory address that has been accessed by the program. In this assignment, you only need to consider the second and the third columns (i e. you don't really need to know the PCs). Cache Simulator You will implement a cache simulator to evaluate different configurations of caches. It should be able to run with different traces files. The followings are the requirements for your cache simulator: 1. Simulate only one level cache L1 2. The cache size, associativity, and block size are input parameters. Cache size and block size are specified in bytes