Can anybody could help me with this question. Please explain it one by one with answer.

Question 3 The instruction pipeline has 5 stages: fetch instruction (FI), decode instruction (DI), fetch operand (FO), execute instruction (EI), and write back (WB). The pipelined microprocessor executes a program consisting of instructions 11 to 111 as shown below. Instructions are issued at a rate of one per clock cycle of 2 nsec. Assume that each pipeline stage takes one clock cycle. 11 12 13 14 15 16 17 18 19 110 111 MOV MOV MOV LOOP SUB ADD MOV JG CONT JLE SUB JMP END MOV Mem1, #2 RO, Mem1 R1, #0 R0, #1 R1, #2 Mem2, R1 LOOP END R1, #5 CONT Mem3, R1 /* 2 Mem1 */ /* [Meml] RO */ /* 0 R1 */ /* (RO) 1 RO */ /* (R1) + 2 R1 */ /* (R1) Mem2 */ /* Jump if (RO)>0 */ /* Jump if (R1) 0 */ /* Jump if (R1)