Can I have help with computer engineering. Please see attached. VHDL

Part I L program to model the circuit whose Using component instantiation of AND and OR gates, write a VHD output expression is given as FA, B, C) A BC. Use the bit/bit vector logic system in your program. Also, write a testbench to test the functionality of this circuit for all input combinations. Part II Designing a 2-bit Comparator in VHDL In this part, you will design a 2-bit magnitude comparator using a hierarchical approach and then develop a testbench for your design. Use the bit/bit vector logic system. The approach to be adopted is outlined below A) Write a VHDL structural model for a 1-bit magnitude comparator by instantiating the necessary logic gates. The inputs to this 1-bit magnitude comparator are X, Y and S X and Y are the data inputs, ie. X and Y are the inputs whose values are compared by the comparator S is the enable input that acts like a master switch for the comparator When S-1, disabled. The outputs of this comparator are EQ (Eq-l only if X-Y and S=l), GT (GT-l only if X-Y and s-1) and LT (LT-1 only if X B and M=1 L = l if and only if AB and M-1 C) Develop a testbench to test your 2-bit comparator design for all input combinations (there will be 16 cases in all, since both A and B are 2-bits wide each). Note The DUT (Design Under Test) must be instantiated within the testbench. Upon simulation, the following message must be printed if there are no errors Test finished" If an error is encountered for a given input combination, then the following message must be printed Test failed" The "Test failed" message must be printed each time an error occurs during the testing process