Question: Can someone fix my code? I have pasted my code along with the original directions. Please paste the entire finished code when done. Thank you!

Can someone fix my code? I have pasted my code along with the original directions. Please paste the entire finished code when done. Thank you! (VHDL)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity signed_multiplier is
Port (
clk : in std_logic; -- Clock signal
rst : in std_logic; -- Reset signal
a_in : in std_logic_vector(7 downto 0); -- Input A (8-bit signed)
b_in : in std_logic_vector(7 downto 0); -- Input B (8-bit signed)
result_out : out std_logic_vector(15 downto 0)-- Output result (16-bit signed)
);
end signed_multiplier;
architecture Behavioral of signed_multiplier is
signal a_reg, b_reg : std_logic_vector(7 downto 0);
signal accumulator : std_logic_vector(15 downto 0) :=(others =>'0');
component multiplier_unit is
Port (
a : in std_logic_vector(7 downto 0);
b : in std_logic_vector(7 downto 0);
product : out std_logic_vector(15 downto 0)
);
end component;
component accumulator_unit is
Port (
clk : in std_logic;
rst : in std_logic;
data_in : in std_logic_vector(15 downto 0);
accumulator_out : out std_logic_vector(15 downto 0)
);
end component;
begin
-- Register A and Register B
process(clk, rst)
begin
if rst ='1' then
a_reg =(others =>'0');
b_reg =(others =>'0');
elsif rising_edge(clk) then
a_reg = a_in;
b_reg = b_in;
end if;
end process;
-- Multiplier Unit
multiplier_inst : multiplier_unit port map(a_reg, b_reg, accumulator(15 downto 0));
-- Accumulator Unit
accumulator_inst : accumulator_unit port map(clk, rst, accumulator, result_out);
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity multiplier_controller is
Port (
clk : in std_logic; -- Clock signal
rst : in std_logic; -- Reset signal
start : in std_logic; -- Start signal to initiate multiplication
done : out std_logic -- Done signal indicating multiplication is complete
);
end multiplier_controller;
architecture Behavioral of multiplier_controller is
type state_type is (IDLE, LOAD_INPUTS, MULTIPLY, ACCUMULATE);
signal current_state, next_state : state_type := IDLE;
signal start_flag, done_flag : std_logic :='0';
begin
process(clk, rst)
begin
if rst ='1' then
current_state = IDLE;
start_flag ='0';
done_flag ='0';
elsif rising_edge(clk) then
current_state = next_state;
start_flag = start;
done_flag ='0';
end if;
end process;
process(current_state, start_flag)
begin
case current_state is
when IDLE =>
if start_flag ='1' then
next_state = LOAD_INPUTS;
else
next_state = IDLE;
end if;
when LOAD_INPUTS =>
-- Code to load inputs into registers
next_state = MULTIPLY;
when MULTIPLY =>
-- Code to trigger multiplication
next_state = ACCUMULATE;
when ACCUMULATE =>
-- Code to accumulate results
next_state = IDLE;
done_flag ='1';
when others =>
next_state = IDLE;
end case;
end process;
done = done_flag;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity multiplier_top is
Port (
clk : in std_logic; -- Clock signal
rst : in std_logic; -- Reset signal
start : in std_logic; -- Start signal for multiplication
a_in : in std_logic_vector(7 downto 0); -- Input A (8-bit signed)
b_in : in std_logic_vector(7 downto 0); -- Input B (8-bit signed)
result_out : out std_logic_vector(15 downto 0)-- Output result (16-bit signed)
);
end multiplier_top;
architecture Behavioral of multiplier_top is
signal done_flag : std_logic;
component signed_multiplier is
Port (
clk : in std_logic;
rst : in std_logic;
a_in : in std_logic_vector(7 downto 0);
b_in : in std_logic_vector(7 downto 0);
result_out : out std_logic_vector(15 downto 0)
);
end component;
component multiplier_controller is
Port (
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
done : out std_logic
);
end component;
begin
multiplier_inst : signed_multiplier port map(clk, rst, a_in, b_in, result_out);
controller_inst : multiplier_controller port map(clk, rst, start, done_flag);
end Behavioral;
Can someone fix my code? I have pasted my code along

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