Can someone fix my code? I pasted my code below and keep getting these errors. Can someone paste the fixed code once it compiles and is able to be ModelSimed. Thank you.

library IEEE;

use IEEE.STD$\_$LOGIC$\_1164.$ALL;

use IEEE.STD$\_$LOGIC$\_$ARITH.ALL;

use IEEE.STD$\_$LOGIC$\_$UNSIGNED.ALL;

entity Memory is

Port $($ Clk : in STD$\_$LOGIC;

Ld$1$ : in STD$\_$LOGIC;

ReadAddr : in STD$\_$LOGIC$\_$VECTOR$(1$ downto $0)$;

WriteAddr : in STD$\_$LOGIC$\_$VECTOR$(1$ downto $0)$;

Memin : in STD$\_$LOGIC$\_$VECTOR$(5$ downto $0)$;

Memout : out STD$\_$LOGIC$\_$VECTOR$(5$ downto $0))$;

end Memory;

architecture Behavioral of Memory is

type memory$\_$array is array $(0$ to $3)$ of std$\_$logic$\_$vector$(5$ downto $0)$;

signal memory$\_$reg : memory$\_$array :$=($others $=>($others $=>\text{'}0\text{'}))$;

begin

process $($Clk$)$

begin

if rising$\_$edge$($Clk$)$ then

if Ld$1=\text{'}1\text{'}$ then

memory$\_$reg$($to$\_$integer$($unsigned$($WriteAddr Memin;

end if;

Memout memory$\_$reg$($to$\_$integer$($unsigned$($ReadAddr$)))$;

end if;

end process;

end Behavioral;

$--$ Process for selecting output based on readAddr

process$($clk$)$

begin

if rising$\_$edge$($clk$)$ then

case readAddr is

when $"00"=>$ Memout register$(0)$;

when $"01"=>$ Memout register$(1)$;

when $"10"=>$ Memout register$(2)$;

when $"11"=>$ Memout register$(3)$;

when others $=>$ Memout XXXXXX$"$; $--$ Handle invalid addresses

end case;

end if;

end process;

$--$ Tri$-$state buffer for output selection

tri$\_$state$\_$select: signal $(2$ downto $0)$;

with tri$\_$state$\_$select select Memout

register$(0)$ when $"001",$

register$(1)$ when $"010",$

register$(2)$ when $"100",$

register$(3)$ when $"111",$

$"$ZZZZZZ$"$ when others;

$--$ Connect tri$-$state buffers based on readAddr

tri$\_$state$\_$select when readAddr $="00"$ else

$"010"$ when readAddr $="01"$ else

$"100"$ when readAddr $="10"$ else

$"111"$ when readAddr $="11"$ else

$"000"$;

end architecture Behavioral;