Can someone please help with the code and test bench in VHDL please and thanks!

Now design a 16-bit 8-to-1 MUX using only 16-bit 2-to-1 MUXes (you can use the one implemented in Problem 1). Data inputs and output should be 16-bit vectors. Your 8-to-1 MUX should be implemented using structural style and should have a three-bit signal for the select line. In your test bench, you should include enough number of test cases to show the correctness of your design. Report: VHDL code, waveforms, and the block diagram of 8-to-1 MUX