Can you help me with this question.The programming language is Verilog ,not VHDL

Design a 2-bit synchronous up/down counter that counts from 0 to 3. Counter must have the reset, up_down and clk ports as an input and 2-bit output port. a) Praw the state diagram for this counter. (Clearly label all states and their transitions) b) Write down the behavioral-Level HDL code. c) Write down a testbench for your code. Test all possible input combinations