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Design a 2-bit synchronous counter of the general form shown in Figure A.49 that counts in the sequence ...,0,3,1,2,0,...,usingDip-ops. This circuit has no external inputs, and the outputs are the ip-op values themselves.

- file:///E n,%20Hamacher.pdf Figure A.48 Sulement for cample in Figure A7 transitions from all pn stalus to the west nnies as neqird by the appliod input x. also shuws the value of the output signal, z, in cach stale Having specified the desired updown counter in general terms, we will now consider its implementation. Two bits are needed to encode the four staes that indicate the cont Let these bits be y high order) andy (low order The states of the counter are determined by the values ofy and yi which we will write ithe form We will assign values to yan for each of te for stares as follows: Su-00, S1-01,52-10, and S3 11 We have chosen the signment such that the talary number yth epresents the count in obnius wa The variables y andy are called the state uriables of the soquetial circuit. Using this stare assiewnen, the sale lable for our example is as shown in Figane A.48 Note that we are using the variabesY and Ylodenoe the DI stae in the samemanner as y2 and are usd o represent the present se Figure A.49 Implementation of the up/down counler. The ouput z is determined as These expressions lead to the circuit shown in Figure A49. It is important to note that we could have chosen a different asignment of yz values to the various states. For example, a possible state asignment is: SO-10, SI-11, S2-01, and S3-0 For a counter circuit, this asignment is less intuitive than the one in Figure A.48, but the resultant circuit will work properly. Different state assignments usually lead to ditferent costs in implementing the circuit (see Problem A.30) A.13.2 TIMING DIAGRAMS To fully understand the operation of the counter circuit, it is useful to consider its timing diagram. Figure A.50 gives an example of a possible sequence of events. It assumes that tate transitions (changes in flip-flop values) oocur on the negative edge of the clock and that the counter starts in state 50 Since , the couster advances to state S1 at o, then toS2ath.and lo S3 at 12. The output ehanges from 1) tol when the unir caters Malt S2. It goes back to 0 when state S3 is reached. At is, the coumler poes to S0. We have assumod thad at this time the inputs changs lo I,causing the counler lo count in the down sonx When the countl again reaches S2, at ds, the ostput z gues to 1 Cur istention in is esample is to use D flip-tops to store the values of the two state variables hewan scessive dlock pulses The uu, Q, oa fli-op is the preaem-stane 1 and x, as indicaled in Figure A.48 From the igune, we see that Nole that all signal changes occur just after the negative edge of the clock, and signals do not change again unkil the negative edge of the next clock pulse. The delay from the clock edge to the time at which variables y change is the propagation delay of the flip flopes used to implement the counter circuit. It is important to noke that the input is also assumed to be controlled by the same clock, and it changes only ncar the heginning of a clock period 4:40 PM O Type here to search 9/28/2018 3