Can you help solve my errors

Homewo Overview

In this assignment modules will be completed that compute $a{2}^s+b>c$ where inputs a and $b$ are

real and inputs $s$ and $c$ are non$-$negative integers. Each module has an output gt$,$ which should be

set to $1$ if the comparison is true and $0$ otherwise. There is also an output ssum which should be

set to $a{2}^s+b.$ What makes this interesting is that the sizes of all inputs are parameters, and that

in the instantiations tested the number of bits in the significands of a and $b$ can be less than the

number of bits in $c.$

The floating point calculations and conversion$($s$)$ are to be done using Chipware modules.

Solving this assignment requires a straightforward application of Verilog techniques for instantiating

modules and wiring them together. It also requires an understanding of when and how to convert

numbers from floating$-$point to integer representations.

As of this writing two modules are to be completed, comp$\_$fp and comp$\_$int. In comp$\_$fp the

greater$-$than comparison is to be done in floating point $($using a Chipware module$)$ and in comp$\_$int

it is to be done using an integer comparison $($using the $>$ operator$).$ file: actual: Fri Oct $420$:$04$:$572024$

: hw$02.$v

assign ssum $=($shifted$\_$exp, a$\_$sig$)+$ b$\_$sig;

xmvlog: $*$E$,$EXPRPA $($hw$02.$v$,95|29)$: expecting a right parenthesis $(\text{'})\text{'})[4\mathrm{.}3][9\mathrm{.}7($IEEE$)].$

assign ssum $=($shifted$\_$exp, a$\_$sig$)+$ b$\_$sig;

l

xmvlog: $*$E$,$MISEXX $($hw$02.$v$,95|36)$: expecting an $\text{'}=\text{'}$ or sign in an assignment $[9\mathrm{.}2($IEEE$)].$

assign ssum $=($shifted$\_$exp, a$\_$sig$)+$ b$\_$sig;

l

xmvlog: $*$E$,$EXPSMC $($hw$02.$v$,95|38)$: expecting a semicolon $(\text{'}$;$\text{'})[6\mathrm{.}1($IEEE$)].$

module worklib.comp$\_$fp:v

errors: $3,$ warnings: $0$

comp$\_$fp #$(.$w$-$c$($w$\_$c$),.$w$\_$s$($w$\_$s$),.$w$\_$exp$($w$\_$exp$),.$w$\_$sig$($w$\_$sig$),.$w$\_$sig$2($w$\_$sig$2)$

$|$

xmvlog: $*$E$,$EXPLPA $($hw$02.$v$,136|15)$: expecting a left parenthesis $(\text{'}(\text{'})[7\mathrm{.}2\mathrm{.}3($AMSLRM$)].$

$.$sum$($ssum$),$

$|$

xmvlog: $*$E$,$EXPRPA$($hw$02.$v$,137|6)$: expecting a right parenthesis $(\text{'})\text{'})[12\mathrm{.}1\mathrm{.}2][8\mathrm{.}6][7\mathrm{.}1][7\mathrm{.}15\mathrm{.}1($IEEE$)].$

$.$gt$(),$

$|$

xmvlog: $*$E$,$EXPLPA $($hw$02.$v$,138|6)$: expecting a left parenthesis $(\text{'}(\text{'})[12\mathrm{.}1\mathrm{.}2][7\mathrm{.}1($IEEE$)].$

$.$a$($a$),$

l

xmvlog: $*$E$,$EXPLPA $($hw$02.$v$,139|6)$: expecting a left parenthesis $(\text{'}(\text{'})[12\mathrm{.}1\mathrm{.}2][7\mathrm{.}1($IEEE$)].$

b$($b$),$

$|$

xmvlog: $*$E$,$EXPLPA $($hw$02.$v$,140|6)$: expecting a left parenthesis $(\text{'}(\text{'})[12\mathrm{.}1\mathrm{.}2][7\mathrm{.}1($IEEE$)].$

$.$s$($s$),$

l

xmvlog: $*$E$,$EXPLPA $($hw$02.$v$,141|6)$: expecting a left parenthesis $(\text{'}(\text{'})[12\mathrm{.}1\mathrm{.}2][7\mathrm{.}1($IEEE$)].$

$.$c$($c$),$

xmvlog: $*$E$,$EXPLPA $($hw$02.$v$,142|6)$: expecting a left parenthesis $(\text{'}(\text{'})[12\mathrm{.}1\mathrm{.}2][7\mathrm{.}1($IEEE$)].$

;

$|$

xmvlog: $*$E$,$EXPLPA $($hw$02.$v$,143|6)$: expecting a left parenthesis $(\text{'}(\text{'})[12\mathrm{.}1\mathrm{.}2][7\mathrm{.}1($IEEE$)].$

module worklib.comp$\_$int:v

errors: $8,$ warnings: $0$

xrun: $*$E$,$VLGERR: An error occurred during parsing. Review the log file for errors with the code $*$E and fix those identified problems to proceed. Exiting

swith code $($status $1).$

TOOL: $,24\mathrm{.}03-s005$: Exiting $on$ Oct $04,2024at20$:$04$:$57CDT(total$: $00$:$00$:$00)////////////////////////////////////////////////////////////////////////////////////$

$///$ Problem $1$

$//$

$///$ Complete scaled$\_$comp$\_$fp so the comparison is done in FP$.$

$//$

$//[]$ Use Chipware modules for floating$-$point operations and conversions.

$//$

$//[]$ Make sure that the testbench does not report errors.

$//[]$ Module must be synthesizable. Use command: genus $-$files syn$.$tcl

$//$

$//[]$ Don't assume any particular parameter values.

$//$

$//[]$ Code must be written clearly.

typedef enum logic $[2$:$0]$

$\{$ Rnd$\_$to$\_$even $=0,$ Rnd$\_$to$\_0=1,$ Rnd$\_$to$\_$plus$\_$inf $=2,$

Rnd$\_$to$\_$minus$\_$inf $=3,$ Rnd$\_$to$\_$near$\_$up $=4,$ Rnd$\_$from$\_0=5\}$

Rnd;

module comp$\_$fp

int w$\_$fp $=1+$ w$\_$exp $+$ w$\_$sig, w$\_$fp$2=1+$ w$\_$exp $+$ w$\_$sig$2)$

$($ output logic gt$,$

output logic $[$w$\_$fp$2-1$:$0]$ ssum,

input uwire $[$w$\_$fp$-1$:$0]$ a$,$ b$,$

input uwire $[$w$\_$s$-1$:$0]$ s$,$

input uwire $[$w$\_$c$-1$:$0]$ c$)$;

logic $[$w$\_$sig$2-1$:$0]$ a$\_$sig, b$\_$sig;

logic $[$w$\_$exp$-1$:$0]$ a$\_$exp, b$\_$exp;

assign a$\_$sig $=\{$a$[$w$\_$sig$-1$:$0],\{$w$\_$sig$2-$w$\_$sig$\{1\text{'}$b$0\}\}\}$;

assign b$\_$sig $=\{$b$[$w$\_$sig$-1$:$0],\{$w$\_$sig$2-$w$\_$sig$\{1\text{'}$b$0\}\}\}$;

assign a$\_$exp $=$ a$[$w$\_$fp$-1$:w$\_$sig$]$;

logic $[$w$\_$exp$-1$:$0]$ shifted$\_$exp;

assign shifted$\_$exp $=$ a$\_$exp $+$ s;

assign ssum $=($shifted$\_$exp, a$\_$sig$)+$ b$\_$sig;

$//[]$ Convert a and b to FP values with w$\_$sig$2-$bit significands.

$//[]$ Compute a $*2**$s$.$

$//[]$ Compute ssum $=$ a$*2**$s $+$ b;

$//[]$ Compute gt $=$ a $*2**$s $+$ b $>$c;

$//[]$ The greater$-$than comparison must be done as FP comparison.

assign ssum $=0$;

assign gt $=1$;

assign gt $=($ssum $>$ c$)?1\text{'}$b$1$ : $1\text{'}$b$0$;

endmodule $//$ Problem $2$

$/$

$///$ Complete scaled$\_$comp$\_$int so the comparison is done as an int.

$1$

I $[]$ Use Chipware modules for floating$-$point operations and conversions.

I$/[]$ Make sure that the testbench does not report errors.

$//[]$ Module must be synthesizable. Use command: genus $-$files syn$.$tcl

$[]$ Don't assume any particular parameter values.

$[]$ Code must be written clearly.

module comp$\_$int

#$($ int w$\_$c $=5,$ w$\_$s $=2,$ w$\_$exp $=5,$ w$\_$sig