Can you please help with task 0-3 need the answers for these quetions:

1-How do you expect the output of a 2-input XOR gate to behave?

2-What tests did you perform to verify your logic circuit?

3-Did the circuit behave as expected? If no, what was wrong?

Task 0-1: Build a 2-input XOR gate using AND/OR/NOT gates in Digital Include a picture of your Digital circuit here: Please comment on the single biggest issue you were facing when designing the circuit. Task 0-3: Export the design and simulate in Verilog Include a picture of your GTKWave simulation (timing diagram) here: Please answer the following questions: 1. How do you expect the output of a 2-input XOR gate to behave? 2. What tests did you perform to verify your logic circuit? 3. Did the circuit behave as expected? If no, what was wrong