CIS $480/580$

Cache: In$-$Class Work $2$

Name: $\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_$

CSU ID: $\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_$

$1.$ Indicate hits$/$misses and updated cache tags for the following cache accesses.

a$.$ The table below shows a series of cache accesses to a direct mapped cache with a write

allocate policy of $$write allocate$.$ Assume the cache is initially empty $($valid bits $=0,$ cache

tags are undefined$),$ and determine whether each access is a hit or miss. Use XXXX for the

cache tag if the cache tag value is undefined.

Access

#

Load$/$Store Addr Tag Cache Line Hit$/$Miss

Cache Tag

for Cache

Line after

Access

$1$ Store $101$

$2$ Load $110$

$3$ Load $110$

$4$ Load $111$

$5$ Load $111$

$6$ Store $101$

b$.$ Repeat part a$,$ but assume a write policy of $$write no allocate.$$

Access

#

Load$/$Store Addr Tag Cache Line Hit$/$Miss

Cache Tag

for Cache

Line after

Access

$1$ Store $101$

$2$ Load $110$

$3$ Load $110$

$4$ Load $111$

$5$ Load $111$

$6$ Store $101$

c$.$ The table below shows a series of cache accesses to a $2-$way set associative cache. Assume a

replacement policy of FIFO. The write policy is $$write no allocate$.$ Assume the cache is

initially empty $($valid bits $=0,$ cache tags are undefined$),$ and determine whether each access

is a hit or miss. Use XXXX for the cache tag if the cache tag value is undefined.

Access

#

Load$/$Store Addr Tag Cache

Line Hit$/$Miss

Cache Tag for Cache

Line after Access

Block $0$ Block $1$

$1$ Load $100$

$2$ Load $110$

$3$ Load $110$

$4$ Load $111$

$5$ Load $111$

$6$ Load $100$

$7$ Load $010$

d$.$ Repeat part c$,$ but assume a replacement policy of LRU.

Access

#

Load$/$Store Addr Tag Cache

Line Hit$/$Miss

Cache Tag for Cache

Line after Access

Block $0$ Block $1$

$1$ Load $100$

$2$ Load $110$

$3$ Load $110$

$4$ Load $111$

$5$ Load $111$

$6$ Load $100$

$7$ Load $010$