Class Activity $4$: Designing Sequential Circuits with JK Flip$-$Flops

Task $1$: Design the Sequential Circuit

State Diagram Analysis:

Analyze the provided a state diagram for the JK Flip Flop

State Table Creation:

Create the state table based on the state diagram.

Boolean Function Derivation:

Simplify the Boolean functions for the combinational circuit using Karnaugh Maps.

Derive the functions for the J and K inputs of each flip$-$flop.

Circuit Diagram:

Draw the complete circuit diagram including the JK flip$-$flops and combinational logic.

Task $2$: Simulate the Circuit

VHDL Code:

Write the VHDL code for the designed sequential circuit.

Include the JK flip$-$flop components and the combinational logic.

Testbench Creation:

Create a testbench to simulate the circuit.

Include test cases that cover all state transitions.

Simulation:

Use EDA Playground to simulate the VHDL code.

Verify the outputs and ensure they match the expected state transitions.