Compare the performance of a single-cycle / multi-cycle / pipelined processor. The delay times are as follows:

Instruction memory access time = 500 ps

Data memory access time = 500 ps

Instruction Decode and Register read = 300 ps

Register write = 200 ps

ALU delay = 300 ps

Ignore the other delays in the multiplexers, wires, etc.

Assume the following instruction mix: 35% ALU, 20% load, 10% store, 25% branch, and 10% jump.

a. Compute the delay for each instruction class for the single-cycle processor.

Instruction Class	Instruction memory	Decode and Reg Read	ALU	Data Memory	Reg WB	Total delay (ns)
ALU
Load
Store
Branch
Jump

b. Compute the clock cycle for the single-cycle processor.

c. Compute the clock cycle for the multi-cycle processor.

d. Compute the average CPI for the multi-cycle processor.

e. What is the speedup factor of the multi-cycle over the single-cycle processor?

f. What is the speedup factor of the pipelined over the single-cycle processor?