$[$Computer Architecture$][$Performance of Single$-$Cycle, Multi$-$Cycle, and Pipelined CPU$]$ Compare the performance of a single$-$cycle processor and a multi$-$cycle

processor. The delay times are as follows:

Instruction memory access time $=500ps$

Data memory access time $=500ps$

Instruction Decode and Register read $=200$ ps

Register write $=200ps$

ALU delay $=100ps$

Ignore the other delays in the multiplexers, wires, etc. Assume a program has

the following instruction mix:

$40\%$ ALU, $5\%$ load, $5\%$ store, $30\%$ branch, and $20\%$ jump.

a$.$ Compute the delay for each instruction class and the clock cycle for the single$-$

cycle processor. $(5$ pts$)$

Clock cycle for the single$-$cycle processor $(5$ pts$)$:

$2.$Compare the performance of a single$-$cycle processor and a multi$-$cycle processor. The delay times are as follows:

Instruction memory access time $=500$ ps

Data memory access time $=500$ ps

Instruction Decode and Register read $=200$ ps

Register write $=200$ ps

ALU delay $=100$ ps

Ignore the other delays in the multiplexers, wires, etc. Assume a program has the following instruction mix:

$40\%$ ALU, $5\%$ load, $5\%$ store, $30\%$ branch, and $20\%$ jump.

A$.$Compute the delay for each instruction class and the clock cycle for the single$-$cycle processor:

Instruction Class Instruction Memeory Decode and Register Read ALU Data Memory Write Back Total Delay

ALU:

Load:

Store:

Branch:

Jump:

B$.$Clock cycle for the single$-$cycle processor:

C$.$Assume that the processor is pipelined. Furthermore, assume that a program has the following instruction mix: $40\%$ ALU, $5\%$ load, $5\%$ store, $30\%$ branch, and $20\%$ jump. Moreover, assume that $90\%$ of the branches will be taken. The CPU stalls $1$ cycle for each jump and $2$ cycles for each taken branch. Compute the average CPI for the pipelined processor due to control hazards only $($base CPI $=1)$: