Compute Multicore EET. There are 3 questions to this problem. Please show all steps. Thank you!

Question 7: Compute Multicore EET (effective execution time You have a 2-core processor device. Each core has an L1 cache memory. There is a common larger L2 cache memory. Each core has the following specification: 1 GHz CPU clock 32-bit wide instruction and data memory 1 clock cycle per instruction Cache memory specifications: . L1 and L2 cache memories: 1ns access time per 32-bit word . L1 page fault requires 64-bytes transferred from L2 cache .Setup time for transfer: 4 clocks Transfer rate: 16 bytes/clock (128-bit wide L1-L2 transfer path) Cache statistics: cache hit rate is 96% (96% of memory access to L1 successful.) cache miss rate is 4% (4% of memory access needs to access L2 cache.) . . Part 1 (4 pts) What is the expected EET for each core + L1 cache, if they are independent, and don't collide? Part 2 (3 pts) What fraction of memory bandwidth is taken up by page fault recovery for both cores together? Part 3 (3 pts) What is the expected EET if on average each core experiences a page fault after the other core's page fault recovery