computer architechture question

151 1. Modify the block diagram for a single-cycle data path so that it can execute the following instruction Note that, the job of the given instruction is to store 'l' or 'O' in a destination register after comparing two source registers. If both source registers are equal it will store 'O' in the destination register otherwise it will store 1. 151 2. a) Find out the required time to execute the following instruction based on the given table of different stages of pipeline. However, you have not implemented forwarding this time. Now draw the timing diagram assuming that you have implemented pipelining. Stage IF ID EX MEM WB Time(ps) 200 150 200 300 150 lw Sso, Sto, Ss1 add Ss2. So, St1 or $s3, Ss3. S12 and $12, Ss1, $s3 addi $t0,$s1,583 151 b) For instructions given in question no 2(a). Find out the total time required in number of cycles. where you will have to implement forwarding. [Note. There is no need to draw the timing diagram] 151 3. a) Consider a cache memory of size 4KB and block size having 4 words (I word = 4 bytes). Determine the miss rate if the following bytes are addressed sequentially. 10. 15, 20, 4090.5000 b) If we change the block size in Q3(a) to 8 words, what effect does it have on the miss rate? Does $3+2) the miss rate increase or decrease? For which principle of locality does it occur? Explain