Question: computer architecture 5. The following code does computation over two vectors. Consider differentexecution scenarios and provide the average number of cycles per iteration for each

 computer architecture 5. The following code does computation over two vectors.

computer architecture

5. The following code does computation over two vectors. Consider differentexecution scenarios and provide the average number of cycles per iteration for each of them. e se DADDIU R4,R1,#800 ; RI-upper bound for X foo: L. D F2,0(RI): (F2) = X(i) MUL.D F2,F2,FO (F2) a X(i) L.D F6,0 (R2) ; (F6) Y(i) DIV. D F6F6F8 ; (F6) = Y(i)/b SUB.D F6,F2,F6 ; (F6) a X(i) -Y(i)/b Number of Clock Cycles Operations FP Multiplication FP Division FP Subtraction Integer 15 DADDIU R1,R1,#8 ; increment X index DADDIU R2, R2,#8 ; increment Y index DSLTU R3,R1,R4 ; test: continue loop? BNEZ R3,foo ; loop if needed Calculation Memory Access Assume a single -issue pipelinenotusing Tomasulo's algorithm. Show how an iteration of the loop would execute without being scheduled by compiler. 5. The following code does computation over two vectors. Consider differentexecution scenarios and provide the average number of cycles per iteration for each of them. e se DADDIU R4,R1,#800 ; RI-upper bound for X foo: L. D F2,0(RI): (F2) = X(i) MUL.D F2,F2,FO (F2) a X(i) L.D F6,0 (R2) ; (F6) Y(i) DIV. D F6F6F8 ; (F6) = Y(i)/b SUB.D F6,F2,F6 ; (F6) a X(i) -Y(i)/b Number of Clock Cycles Operations FP Multiplication FP Division FP Subtraction Integer 15 DADDIU R1,R1,#8 ; increment X index DADDIU R2, R2,#8 ; increment Y index DSLTU R3,R1,R4 ; test: continue loop? BNEZ R3,foo ; loop if needed Calculation Memory Access Assume a single -issue pipelinenotusing Tomasulo's algorithm. Show how an iteration of the loop would execute without being scheduled by compiler

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