computer architecture and orgnization

5.12 Multilevel caching is an important technique to overcome the limited amount of space that a first-level cache can provide while still maintaining its speed. Consider a processor with the following parameters: Main Base CPI, No Proceso First-level Cache Second level Miss Rate with Second Second Lawl Cache Miss Rate with Second Level Menny Memory Speed Access Miss Rate per Cache, Direct Level Cachw. Dret Statis FighWay Set Cache, Eigh-Way Set Instruction Mapped Speed Mapped Associative Speed Time Associate 1.5 100 7% 12 cycles 28 cycles 1.5% **First Level Cache miss rate is per instruction. Assume the total number of L1 cache misses (instruction and data combined) is equal to 7% of the number of instructions, 14A 5.12.3 [20] In older processors, such as the Intel Pentium or Alpha 21264, the second level of cache was external (located on a different chip) from the main processor and the first-level cache. While this allowed for large second-level caches, the latency to access the cache was much higher, and the bandwidth was typically lower because the second-level cache ran at a lower frequency. Assume a 512 KiB off-chip second- level cache has a miss rate of 4%. If each additional 512 KiB of cache lowered miss rates by 0.7%, and the cache had a total access time of 50 cycles, how big would the cache have to be to match the performance of the second-level direct-mapped cache listed above