Computer Architecture

Consider a pipeline in a processor that has 5 stages: (1) instruction fetch 120 ns, (2) instruction decode 80 ns (3) memory read 60 ns (4) instruction execution 40 ns and (5) register write 75 ns. The times required in each stage are shown following the name of the stage. For example, the instruction fetch requires 120 ns to complete. Assume that every instruction in the instruction set requires the use of all stages of the pipeline. Also assume that the stages of the pipeline are clocked with a common clock. This means that all information moves synchronously through the pipeline from one stage to the next based on a single clock signal dictating when information advances from one stage to the next. (i) Identify the execution time of a 5000-instruction program without pipelining.

(ii) What can you infer on the latency of an instruction flowing through the pipeline? (Remember that you have a common clock)

(iii) Since all stages of the pipeline are clocked with a single clock, interpret the fastest frequency of the clock for this pipeline.

(iv) Draw your conclusion on the idealised throughput of the pipeline. (Assume that there are no hazards between instructions).