Problem $1$

Consider the following MIPS code.

I$0$: Iw $\backslash$$s$3,0(\backslash$$s$2)\backslash$# LDW $\backslash$$s$3=$ M$[\backslash$$s$2+0]$

I$1$: Iw $\backslash$$s$1,12(\backslash$$s$4)\backslash$#LDW $\backslash$$s$1=$ M$[\backslash$$s$1=$ M$[\backslash$$s$4+12]$

I$2$: $\backslash (\backslash$quad $\backslash )$ add $\backslash$$s$5,\backslash$$s$1,\backslash$$s$3\backslash$# ADD $\backslash$$s$5=\backslash$$s$1+\backslash$$s$3$

I$3$: beq $\backslash$$s$6,\backslash$$s$7,$ L$1\backslash$# IF $(\backslash$$s$6=\backslash$$s$7)$ goto L$1$

$14$: $\backslash (\backslash$quad $\backslash )$ sw $\backslash$$s$5,0(\backslash$$s$3).\backslash (\backslash$quad $\backslash )\backslash$#STW M$[\backslash$$s$3+0]=\backslash$$s$5$

$15$: L$1$: sw $\backslash$$s$5,12(\backslash$$s$4)\backslash$#STW M$[\backslash$$s$4+12]=\backslash$$s$5$

A$)$ Suppose a MIPS processor uses the simple $5-$stage pipeline, where the stages are instruction fetch $($IF$),$ instruction decode and operand fetch $($ID$),$ execute and calculate address $($EX$),$ memory access $($M$),$ and write back $($WB$).$ In addition, suppose that:

$-$ The instruction and data cache are unified and can only support one read or write or instruction fetch operation each cycle $($no overlap of M and IF in the same cycle $($on the column$)$ if the instructions involved are Iw$/$sw in M stage and IF for the other instruction$).$The pipeline does not have "forwarding" hardware. Thus, if an instruction $(\backslash (\backslash$mathrm$\{$i$\}+1\backslash ))$ relies on a value written into a register by an instruction $($i$),$ then the execute stage for $\backslash ((\backslash$mathrm$\{$i$\}+1\backslash ))$ cannot proceed until the register write stage for $($i$)$ has completed.In the absence of hazards, a new instruction can be fed to the pipeline every cycle.

How many cycles does this code take to complete? Use the table below. B$)$ Suppose that the MIPS processor with the $5-$stage pipeline from part A$).$ In addition, suppose that:

$-$ The instruction and data cache are split allowing the overlap of instruction fetch with read$/$write data to the cache

$-$ The pipeline has hazard detection and forwarding.

How many cycles does this code take to complete? Use the table below.

cycles C$)$ Suppose now that the Execution stage of the pipeline is split into two stages E$1$ and E$2$ and that instruction $($i$+1)$ cannot use E$1$ until instruction $($i$)$ released E$2,$ or more general E$1$ cannot be used again until E$2$ is finished processing. Using the assumptions from part B$),$ how many cycles does this code take to complete? Use the table below.