Computer Architecture Pipelining

Reference this diagram.

 Make a change to both executions. Make the ALU take 5ns rather that the 4ns as shown on the figure. Neatly redraw the diagram with the new ALU time. Remember every time block on the pipelined execution must be the same. 80 column plain text or print it yourself. After you did that, What is the speedup when a large number of instructions are executed? 

Diagram: Single cycle execution 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 ns I IF I reg I ALU DATA reg I IF reg ALU DATA reg IF reg ALU DATA. reg I Pipelined Execution IF reg I ALU DATA reg reg ALU IF DATA reg reg AL IF DATA reg I 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38ns