computer architecture (please solve as soon as possible)

Question 3 (6 points) A microprocessor has a memory addition instruction. The instruction has five stages: fetch opcode (2 bus cycles), fetch operand address (2 bus cycles), fetch operand (2 bus cycles), add a value (4 bus cycles), and store operand (3 bus cycles). By what amount (in percent) will the duration of the instruction increase if we have to insert one bus wait state in each memory read and write operation? (4 points)