computer architecture

solve the parts without 5.25.1

use or a write burrer. 5.25 Cache coherence concerns the views of multiple processors on a given cache block. The following data show two processors and their read/write operations on two different words of a cache block X (initially X[0=X[1]=0). P1 P2 10 t 10 - 15 tr 5.25.1 [15] List the possible values of the given cache block for a correct cache coherence protocol implementation. List at least one more possible value of the block if the protocol doesn't ensure cache coherency. 5.25.2 [15] For a snooping protocol, list a valid operation sequence on each processor/cache to finish the above read/write operations. 5.25.3 [10] What are the best-case and worst-case numbers of cache misses needed to execute the listed read/write instructions? Memory consistency concerns the views of multiple data items. The following data show two processors and their read/write operations on different cache blocks (A and B initially 0). P1 P2 5.25.4 [15] List the possible values of C and D for all 974 page 455. implementations that ensure both consistency assumptions on 5.25.5 [15] List at least one more possible pair of values for C and D if such assumptions are not maintained. 5.25.6 [15] For various combinations of write policies