$5\mathrm{.}25$ Cache coherence concerns the views of multiple processors on a given cache

block. The following data show two processors and their read$/$write operations on

two different words of a cache block $x($initially $x[0]=x[1]=0).$

$5\mathrm{.}25\mathrm{.}1[15]$$$5\mathrm{.}10>$ List the possible values of the given cache block for a correct

cache coherence protocol implementation. List at least one more possible value of

the block if the protocol doesn't ensure cache coherency.

$5\mathrm{.}25\mathrm{.}2[15]$$$5\mathrm{.}10>$ For a snooping protocol, list a valid operation sequence on

each processor$/$cache to finish the above read$/$write operations.

$5\mathrm{.}25\mathrm{.}3[10]$$$5\mathrm{.}10>$ What are the best$-$case and worst$-$case numbers of cache

misses needed to execute the listed read$/$write instructions?

Memory consistency concerns the views of multiple data items. The following data

show two processors and their read$/$write operations on different cache blocks $($A

and B initially $0).$

$5\mathrm{.}25\mathrm{.}4[15]$$$5\mathrm{.}10>$ List the possible values of $C$ and $D$ for all implementations

that ensure both consistency assumptions on page $476.$

$5\mathrm{.}25\mathrm{.}5[15]$$$5\mathrm{.}10>$ List at least one more possible pair of values for $C$ and $D$ if

such assumptions are not maintained.

$5\mathrm{.}25\mathrm{.}6[15]$$$$5\mathrm{.}3,5\mathrm{.}10>$ For various combinations of write policies and write

allocation policies, which combinations make the protocol implementation

simpler?