Computer organization, design and write Verilog code

In this assignment, you are required to design, implement and simulate a divider unit that can perform division on unsigned binary numbers. The unit has an 4-bit input called divisor, a 8-bit input called dividend, an input clock, a 1-bit output called valid, a 4-bit output called remainder and a 4-bit output quotient. The valid bit is set to indicate that the result on the quotient and remainder output are valid. To accomplish the task, you need to provide two alternative designs for the divider unit. You need to compare the two designs based on the performance (timing) and hardware cost and identify the best design Your design should be implemented and tested on the Quartus design software