Computer Science

Please provide the complete step by step solution With all the code

I need to do this State machine in veriolg, please give me the code, for programing it you

must do the syntehesis process for Each state variable, and also for the outputs, do the

counter and implement it all in verilog please.

Where is the output of a counter that resets to $0$ if the signal is high, and

counts as long as is low and is high: