Computer Science

Please provide the complete step by step solution with all the code

I need to make the structural implementation level modeling $($ONLY USING THE FLIP FLOPS AND LOGIC GATES $)$ on Verilog of this machine. Please use the

attached schematics, the set state variables and all that is given in the pictures for

programming it$,$ please provide all the code, as well as a testbench, please separate each

module in a file.

Where is the output of a counter that resets to $0$ if the signal is high, and

counts as long as is low and is high: