Computer Science Verilog

Provide the complete code including the generator, the receiver and a testbench please! Please make sure it works before submitting your answer!

Design of an I$2$C transaction generator and receiver

Design an I$2$C transaction generator according to the specifications in the document I$2$C$-$bus Specification and User Manual, revision $7\mathrm{.}0.$

Interfaces of the Generator:

a$)$ CLK $$ This is an input that comes from the CPU with a certain frequency. The active edge is the rising edge.

b$)$ RESET $$ Input to reset the generator. If RESET$=1,$ the generator works normally. Otherwise, the generator returns to its initial state and all outputs go to zero.

c$)$ START$\_$STB $$ A one$-$clock cycle strobe pulse indicating that the CPU wants to initiate an I$2$C transaction.

d$)$ RNW $$ Read not write. This signal indicates the direction of the transaction the CPU wants to execute. When RNW$=1,$ it is a read transaction; when RNW$=0,$ it is a write transaction.

e$)$ I$2$C$\_$ADDR$[6$:$0]$ This input comes from a CPU register and contains the address of the I$2$C transaction receiver.

f$)$ SCL $$ I$2$C clock output. The active edge of the SCL signal is the rising edge. The generator must generate SCL at $25\%$ of the input CLK frequency.

g$)$ SDA$\_$OUT $$ Serial data output. Must behave according to the I$2$C protocol for START, STOP, and read$/$write transactions.

h$)$ SDA$\_$OE $$ Enable signal for SDA$\_$OUT. Set to $1$ when the generator controls the I$2$C bus, and $0$ when the receiver controls it$,$ according to protocol specifications.

i$)$ SDA$\_$IN $$ Serial input from the tester. Must behave as per the I$2$C protocol for ACK signals and providing input data during read transactions.

j$)$ WR$\_$DATA$[15$:$0]$ Parallel input containing the $16$ bits to be sent through I$2$C during a write transaction.

k$)$ RD$\_$DATA$[15$:$0]$ Output producing the $16$ bits received from the I$2$C transaction receiver during a read transaction on SDA$\_$IN$.$ After receiving the $16$ bits, the generator must send a STOP condition per the I$2$C protocol.

Receiver Interfaces:

l$)$ CLK $$ Input clock from the CPU with a rising active edge.

m$)$ RESET $$ Resets the receiver. If RESET$=1,$ the receiver operates normally. Otherwise, it resets to the initial state.

n$)$ I$2$C$\_$ADDR$[6$:$0]$ Input address to verify that the received transaction matches the receiver$$s address.

o$)$ SCL $$ Input clock for I$2$C$.$ The active edge is the rising edge.

p$)$ SDA$\_$OUT $$ Serial output that must follow I$2$C protocol for START, STOP, and read$/$write transactions.

q$)$ SDA$\_$OE $$ Enable signal for SDA$\_$OUT during certain parts of the transaction.

r$)$ SDA$\_$IN $$ Serial input sent from the receiver to the generator, used for ACK and providing data during reads.

s$)$ WR$\_$DATA$[15$:$0]$ Parallel output containing the $16$ bits received via I$2$C during a write transaction.

t$)$ RD$\_$DATA$[15$:$0]$ Parallel input providing the $16$ bits to be sent during a read transaction through SDA$\_$IN$.$