Consider a $1GHz$ machine with $16-$bit address bus, a direct$-$mapped L$2$ cache of $1KB$ and an $2-$way associative $L1$ cache of $512B$ with the following access times: $1\mathrm{.}2$ miss penalty: $250$ cycles, $L2$ hit time: $20$ cycles, $L1$ hit time $1$ cycles.

a$.$ Calculate the average memory access time for the system if the memory instructions are $10\%$ and hit rates are $50\%$ for $L1$ and $80\%$ for $L2.$

b$.$ If the cache block size is $8$ bytes, how many block positions does each cache have? c$.$ For the following address references, write the tag and the cache index $($line$)$ for both caches: $044B4,02$ AE$3,0137,062E5.$ Also, indicate if any pair of these addresses result will share the same block position in any of the two caches. Use the table at the end to tabulate your answers.

$\backslash$table$[[$Address$,0$x$44$B$4,0$x$2$AE$3,0$x$137,0$x$62$E$5],[$L$2$ Cache,,$],[$Tag$,,,,],[$Line ID$,,,,],[$L$1$ Cache,,,,$],[$Tag$,,,,],[$Line ID$,,,,]]$