Consider a $256K16$ RAM chip.

$($a$)$ What is the size of memory $($in bytes$)$ provided by one $256K16$ RAM chip?

$($b$)$ How many data lines $(m)$ and address lines $(n)$ for the RAM chip above?

$($c$)$ Assume that the $256K16$ RAM chip uses coincident decoding to select one RAM

cell, where a $11-$to$-2048-$line decoder is used as the row decoder. What is the size of

the column decoder in the RAM chip?

$($d$)$ Consider the $4^{th}$ to $6^{th}$ digits of your student ID as a number $A$ in hexadecimal

representation. The $12-$bit binary representation of $A,$ appended with all $0$ s in front of

$A$ to form an $n-$bit address line, is the address input to the RAM chip above.

$($i$)$ Write down the $n-$bit representation of the address input $($binary format$)$ to the

RAM chip.

$($ii$)$ Determine the row and column selection lines that are enabled with the above

input address. Specify your results in decimal values.

$($e$)$ Suppose a large memory, which has $16-$bit word, is constructed by $p$ pieces of $256K$

$16$ RAM chips above. The capacity of the large memory is $S$ bytes, where $S$ is

determined by the $7^{th}$ digit of your student ID:

use the following student ID to

solve this question $21084996$ A

$($i$)$ How many words are stored in the large memory? Hence, write down the

number of address lines for the large memory.

$($ii$)$ Calculate the value of $p$ above.

$($iii$)$ How many of the address lines are connected to the address inputs of all RAM

chips? How many of them are connected to the decoder which produces the

Chip Select inputs for the RAM chips?

$($iv$)$ Specify the size of the decoder used in the large memory to produce the Chip

Select inputs for the RAM chips.

$($v$)$ Describe the changes in the design of the large memory if the word size, and

subsequently the capacity of the large memory are both doubled.