Consider a 2 to 4 decoder with a validation input, e If e is idle, all outputs will be set to 0, otherwise the selected output will be set to 1 The interface and decoder module are provided below a) Construct, using the Verilog language, the detailed architecture of dec 2s decoder implemented with NAND gates b) Write a testbench for non exhaustive verification of the mode dec 2s previously implemented, according to the schedule below si so dec 25 he 03 02 01 00 module dec 2s ( input (1 0 S, input e, output 3 0 o ) s 1 s 0 e INAND NAND NAND NAND y O y 1 y 2 y 3 yioyf1y y3 S 2'ho 2'h2 2'h1 2'h32'h02'h1 2'h32'h2 2'h1 2'ho e 2 3

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Question: Consider a 2-to-4 decoder with a validation input, e. If e is idle, all outputs will be set to 0, otherwise the selected output will

Consider a 2-to-4 decoder with a validation input, e. If e is idle, all outputs will be set to 0, otherwise the selected output will be set to 1. The interface and decoder module are provided below:

Consider a 2-to-4 decoder with a validation input, e. If e is

a) Construct, using the Verilog language, the detailed architecture of dec_2s decoder implemented with NAND gates.

idle, all outputs will be set to 0, otherwise the selected output

b) Write a testbench for non-exhaustive verification of the mode dec_2s previously implemented, according to the schedule below:

will be set to 1. The interface and decoder module are provided

si so dec_25 he 03 02 01 00 module dec_2s ( input (1:0] S, input e, output [3:0] o ); s[1] s[0] e INAND NAND NAND NAND y[O] y[1] y[2] y[3] yioyf1y] y3 S 2'ho 2'h2 2'h1 2'h32'h02'h1 2'h32'h2 2'h1 2'ho e 2/3

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