Question: Consider a 32-bit memory address computer that has an on-chip 4-way set-associative cache of 16-KBytes. The cache block size is 16 Bytes. (1) How is

Consider a 32-bit memory address computer that has an on-chip 4-way set-associative cache of 16-KBytes. The cache block size is 16 Bytes.

(1) How is the 32-bit memory address divided into three fields for the cache mapping.

(2) For memory address ABCDE8F8 in a hexadecimal representation, where is the block located in the cache in this 4-way set-associative?

(3) Where is the block located in a 4-way multicolumn cache?

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