Consider a cache with the following information

The cache has a total of 2048 bytes, which are divided into 128 blocks with 16 bytes in each block

The main memory has a total of 65536 bytes, which are divided into 4096 blocks with 16 bytes in each block

The main memory uses byte addressing, and thus a memory address has a total of 16 bits

The cache uses 4-way (i.e., k=4) set-associative mapping and LRU replacement.

The total number of sets in the cache is( ) , and the number of bits in a tag associated with a cache block is ( )

Consider the following five read requests for bytes at the following addresses.

request 1 for the byte at address 0x0210

request 2 for the byte at address 0x0410

request 3 for the byte at address 0x0610

request 4 for the byte at address 0x0810

request 5 for the byte at address 0x0214

request 6 for the byte at address 0x0A10

All of these addresses correspond to cache set 1, and thus we consider only case set 1. Initially, we have the following information for cache set 1

cache set	cache block	Valid	tag	counter
1	4	0	n/a	0
1	5	0	n/a	0
1	6	0	n/a	0
1	7	0	n/a	0

after executing read request 1, we have

cache set	cache block	Valid	tag (binary)	counter (decimal)
1	4	1	0b
1	5	0	n/a	0
1	6	0	n/a	0
1	7	0	n/a	0

after executing read request 2, we have

cache set	cache block	Valid	tag (binary)	counter (decimal)
1	4	1	0b
1	5	1	0b
1	6	0	n/a	0
1	7	0	n/a	0

after executing read request 3, we have

cache set	cache block	Valid	tag (binary)	counter (decimal)
1	4	1	0b
1	5	1	0b
1	6	1	0b
1	7	0	n/a	0

after executing read request 4, we have

cache set	cache block	Valid	tag (binary)	counter (decimal)
1	4	1	0b
1	5	1	0b
1	6	1	0b
1	7	1	0b

after executing read request 5, we have

cache set	cache block	Valid	tag (binary)	counter (decimal)
1	4	1	0b
1	5	1	0b
1	6	1	0b
1	7	1	0b

after executing read request 6, we have

cache set	cache block	Valid	tag (binary)	counter (decimal)
1	4	1	0b
1	5	1	0b
1	6	1	0b
1	7	1	0b