Consider a 3-input (A, B, C) XNOR logic:

1. Write out the logic function.
2. Sketch a transistor-level schematic with transistor widths to achieve equal rise and fall resistance equal to that of a unit inverter. Assume that you have both the true and complementary versions of the inputs available. Please use no more than 8 NMOS and 8 PMOS transistors in your schematic.
3. Compute the logical effort of each input and parasitic delay of the 3-input XNOR gate you designed. You can combine each true and complementary as one input in calculating logical effort. Please show detailed analysis.