Consider a $4-$bit ripple carry adder and the following delays: $2-$input XOR gate delay of $2$ ns$,2-$

input OR or AND gate delay of $1$ns$,$ flip flop propagation delay $0\mathrm{.}5$ ns$,$ flip flop setup delay $0\mathrm{.}5$ ns$.$ In

how many stages do you need to pipeline the above adder in order to improve its throughput

more than $3$ times? What is the latency of the pipelined and the unpipelined versions of the adder