Consider a computation running on a machine with a $1$ GHz clock, $6-$word cache line, single cycle access to the cache, and $100$ ns latency to DRAM. The computation has a cache hit ratio at $1$ KB of $30\%$ and at $32$ KB of $80\%.$ Consider three cases: $(1)$ a single threaded execution without caches, $(2)$ a single threaded execution in which the entire cache is available to the serial context, and $(3)$ a multithreaded execution with $32$ threads where each thread has a cache residency of $1$ KB$.$ Calculate the required bandwidths for all the three cases respectively.