. Consider a direct-mapped cache design for a byte-addressable memory. The processor accesses 32- bit word from the cache using the following bits of the 32-bit address: Tag Index Offset i). 31-10 9-5 4-2 ii). 31-12 11-6 5-2 For each configuration i) and ii), Why does the offset start from bit 2 of the 32-bit address? What is the cache line size (in words)? How many entries (cache lines) does the cache have?