$3.$ Consider a direct$-$mapped cache design for a byte$-$addressable memory. The processor accesses $32-$bit word from the cache using the following bits of the $32-$bit address: Tag $31-12$ Index Offset $11-87-2($a$)$ Why does the offset start from bit $2$ of the $32-$bit address? $($b$)$ What is the cache line size $($in words$)?($c$)$ How many entries $($cache lines$)$ does the cache have?