Consider a hypothetical machine having both instructions

and data are $16$ bits long and have instruction format as below.

Assume the list of opcodes as follows:

$\backslash$table$[[0111,$Load AC from memory$],[0100,$Store AC to memory$],[1011,$Subtract to AC from memory$],[1000,$Load IOBR from memory$],[0001,$Store IOBR to memory$]]$

Depict an Instruction Cycle with all the necessary steps for the execution of a Subtraction operation of two $16-$bit data using above mentioned opcode characteristics, The initial content of Memory and CPU registers are shows below.

$\backslash$table$[[$Memory$,$CPU registers$],[300,\backslash$table$[[7,9,2,2]],$PC$],[301,,AC$